Verification Pattern Generation for Core-Based Design Using Port Order Fault Model
نویسندگان
چکیده
The lack of information about core’s internal structure is The designers must rely solely on the test set distributed by the core provider. Sometimes the stuck at fault (SAF) model and automatic test pattern generation (ATPG) are used to generate test vectors for those pre-defined blocks. However, a SAF test set could waste lots of time to verify the pre-verified internal structure of the cores. Therefore, in order to reduce the core-based design verification time, we should adopt the connectivitybased port order fault (POF) model instead of the stuck at fault model. In this paper, we compare the POF model with the SAF model and propose a method that the POF test set for functional verification can be generated by using the SAF-based ATPG tools with proper assignment of don’t care terms in inputs.
منابع مشابه
On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model
Embedded cores are being increasingly used in the design of large System-on-a-Chip (SoC). Because of the high complexity of SoC, the design verification is a challenge for system integrator. To reduce the verification complexity, the port order fault (POF) model proposed in [1] has been used for verifying core-based designs and the corresponding verification pattern generation have been develop...
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